The present invention relates to a semiconductor device and a manufacturing method thereof, and particularly to a technology which is effective when applied to the manufacturing of a semiconductor element having a metal silicide layer.
With the increasing integration of semiconductor devices, a field effect transistor (MISFET: Metal Insulator Semiconductor Field Effect Transistor) has been scaled down according to a scaling rule. However, the resistances of a gate electrode and source/drain regions increase to result in the problem that, even when the field effect transistor is scaled down, a high-speed operation cannot be obtained. To solve the problem, a Salicide (Self Aligned Silicide) technique has been studied in which a low-resistance metal silicide layer such as, e.g., nickel silicide layer or cobalt silicide layer is formed by self-alignment over a surface of each of a conductive film forming the gate electrode and semiconductor regions forming the source/drain regions to thereby reduce the resistances of the gate electrode and the source/drain regions.
In Japanese Unexamined Patent Publication No. 2010-114449 (Patent Document 1), it is disclosed that a silicide layer containing NiSi (nickel monosilicide) and retaining phase stability and film stability even at a high temperature is formed over the main surface of a semiconductor substrate. It is also disclosed that the silicide layer described above contains, e.g., Pt (platinum) or the like.